june 2013 FDD86113LZ n-channel shielded gate powertrench ? mosfet ?2011 fairchild semiconductor corporation 1 www.fairchildsemi.com FDD86113LZ rev. c1 FDD86113LZ n-channel shielded gate powertrench ? mosfet 100 v, 5.5 a, 104 m features ? shielded gate mosfet technology ? max r ds(on) = 104 m at v gs = 10 v, i d = 4.2 a ? max r ds(on) = 156 m at v gs = 4.5 v, i d = 3.4 a ? hbm esd protection level > 6 kv typical (note 4) ? high performance trench technology for extremely low r ds(on) ? high power and current handling capability in a widely used surface mount package ? 100% uil tested ? rohs compliant general description this n-channel logic level mosfets are produced using fairchild semiconductor?s advanced powertrench ? process that incorporates shielded gate technology. this process has been optimized for the on-state resistance and yet maintain superior switching performance. g-s zener has been added to enhance esd voltage level. application ? dc-dc conversion s g d g s d to-252 d-pak (to-252) mosfet maximum ratings t c = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 100 v v gs gate to source voltage 20 v i d drain current -continuous t c = 25 c 5.5 a -continuous t a = 25 c (note 1a) 4.2 -pulsed 15 e as single pulse avalanche energy (note 3) 12 mj p d power dissipation t c = 25 c 29 w power dissipation t a = 25 c (note 1a) 3.1 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case (note 1) 4.3 c/w r ja thermal resistance, junction to ambient (note 1a) 96 device marking device package reel size tape width quantity FDD86113LZ FDD86113LZ d-pak(to-252) 13 ?? 12 mm 2500 units
FDD86113LZ n-channel shielded gate powertrench ? mosfet ?2011 fairchild semiconductor corporation 2 www.fairchildsemi.com FDD86113LZ rev. c1 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 100 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 72 mv/c i dss zero gate voltage drain current v ds = 80 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 10 a v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a11.53v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -5 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 4.2 a 87 104 m v gs = 4.5 v, i d = 3.4 a 116 156 v gs = 10 v, i d = 4.2 a,t j = 125 c 142 170 g fs forward transconductance v ds = 5 v, i d = 4.2 a 9 s c iss input capacitance v ds = 50 v, v gs = 0 v, f = 1mhz 213 285 pf c oss output capacitance 55 75 pf c rss reverse transfer capacitance 2.4 5 pf r g gate resistance 1.4 t d(on) turn-on delay time v dd = 50 v, i d = 4.2 a, v gs = 10 v, r gen = 6 3.6 10 ns t r rise time 1.3 10 ns t d(off) turn-off delay time 9.7 20 ns t f fall time 1.6 10 ns q g(tot) total gate charge v gs = 0 v to 10 v v dd = 50 v, i d = 4.2 a 3.7 6 nc q g(tot) total gate charge v gs = 0 v to 4.5 v 1.9 3 q gs gate to source charge 0.6 nc q gd gate to drain ?miller? charge 0.7 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 4.2 a (note 2) 0.88 1.3 v v gs = 0 v, i s = 1.7 a (note 2) 0.80 1.2 t rr reverse recovery time i f = 4.2 a, di/dt = 100 a/ s 31 49 ns q rr reverse recovery charge 20 33 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0 %. 3. starting t j = 25 c, l = 1 mh, i as = 5 a, v dd = 90 v, v gs = 10 v. 4. the diode connected between gate and source serves only as protection against esd. no gate overvoltage rating is implied. 40 c/w when mounted on a 1 in 2 pad of 2 oz copper a) 96 c/w when mounted on a minimum pad of 2 oz copper b)
FDD86113LZ n-channel shielded gate powertrench ? mosfet ?2011 fairchild semiconductor corporation 3 www.fairchildsemi.com FDD86113LZ rev. c1 typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 3 6 9 12 15 v gs = 2.5 v v gs = 4.5 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 3 v v gs = 3.5 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on-region characteristics figure 2. 03691215 0 1 2 3 4 v gs = 3.5 v v gs = 4.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 3 v v gs = 2.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i d = 4.2 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 0 100 200 300 400 t j = 125 o c i d = 4.2 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0123456 0 3 6 9 12 15 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 20 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDD86113LZ n-channel shielded gate powertrench ? mosfet ?2011 fairchild semiconductor corporation 4 www.fairchildsemi.com FDD86113LZ rev. c1 figure 7. 01234 0 2 4 6 8 10 i d = 4.2 a v dd = 25 v v dd = 50 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 75 v gate charge characteristics figure 8. 0.1 1 10 100 1 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 2 1 2 3 4 5 6 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 2 4 6 8 10 12 limited by package v gs = 4.5 v r t jc = 4.3 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . g a t e l e a k a g e c u r r e n t v s gate to source voltage 0 5 10 15 20 25 30 35 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 v gs = 0 v t j = 25 o c t j = 125 o c v gs , gate to source voltage (v) i g , gate leakage current (a) figure 12. 0.1 1 10 100 400 0.05 0.1 1 10 20 100 p s 10 ms dc 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t jc = 4.3 o c/w t c = 25 o c f o r w a r d b i a s s a f e operating area typical characteristics t j = 25 c unless otherwise noted
FDD86113LZ n-channel shielded gate powertrench ? mosfet ?2011 fairchild semiconductor corporation 5 www.fairchildsemi.com FDD86113LZ rev. c1 figure 13. single pulse maximum power dissipation 10 -5 10 -4 10 -3 10 -2 10 -1 1 10 100 1000 2000 p (pk) , peak transient power (w) single pulse r t jc = 4.3 o c/w t c = 25 o c t, pulse width (sec) figure 14. 10 -5 10 -4 10 -3 10 -2 10 -1 1 0.01 0.1 1 2 single pulse r t jc = 4.3 o c/w duty cycle-descending order normalized thermal impedance, z t jc t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t jc x r t jc + t c junction-to-case transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
FDD86113LZ n-channel shielded gate powertrench ? mosfet ?2011 fairchild semiconductor corporation 6 www.fairchildsemi.com FDD86113LZ rev. c1 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairch ild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life su pport device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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